The present invention relates to a charge-coupled device (CCD) type image sensor, and more particularly, to an MOS output circuit section of a CCD image sensor employing a floating diffusion-type amplifier within a signal detection section.
A CCD has a very simple structure comprised of a plurality of MOS transistors formed in a regular array on the surface of a semiconductor substrate. Each MOS transistor in the array assumes one of two states on the basis of a voltage applied to its gate. The first state, a non-balanced state, is characterized by deep depletion layer extending through a portion of a surface of the semiconductor substrate. The second state, a balanced state, is characterized by an accumulation of minority carriers. Digital logic states of "0" or "1" can be respectively defined as corresponding to each of these two states. In this manner, the CCD can be used as a digital memory device, or as a signal processing device adapted to process digital signals. Additionally, the voltage signal applied to the respective MOS transistor gates may be continuously varied between the non-balanced and balanced states in which case the CCD may function as an analog device. Functioning in either its analog or digital modes, the CCD may be adapted for use as an image sensor.
A typical image sensor operates by collecting or distributing electrical charge on the basis of photoelectric energy incident to light received by the sensor. In other words, the image sensor operates by photoelectrically converting an optical signal into an electrical signal. In a CCD type image sensor, electrical charge is accumulated in response to an optical signal. The accumulated charge is then sequentially transferred through and output from the CCD by a pulse clocking signal. The charge is transferred as an output signal via an output section to external circuitry which realizes an image corresponding to the received light.
A floating diffusion-type amplifier (FDA) is commonly used within the output section of a CCD type image sensor. An FDA is used to handle the output charge which may be produced at a relatively high level. Furthermore, an FDA introduces very little noise into the output signal.
FIG. 1 is a schematic plan view illustrating an output section of a CCD having a conventional FDA. The output section shown in FIG. 1 is exemplary of the type of circuit disclosed in U.S. Pat. No. 4,660,064 to Hamasaki et al, and is characterized by a floating diffusion region and a precharge diffusion region which are aligned so as to increase the output gain.
Within FIG. 1, output gate electrode 17 is formed on one end of a CCD transfer section 1. A precharge MOS transistor (or reset MOS transistor) is comprised of a floating diffusion region 18, a precharge gate 25, and a precharge drain 23. A first drive MOS transistor M1 is comprised of a source region 20, a drain region 21, and a gate electrode 19 connected to floating diffusion region 18 which is bordered by a channel stopper region 22. Naturally a plurality of such structures is formed in an array, but for purposes of this explanation only a single structure is described in FIG. 1.
FIG. 2 is a diagram showing an equivalent circuit for the output section of a CCD having a conventional FDA. As shown in FIG. 2, electrical charge flows from the output terminal of CCD transfer section 1 to diode 2 in the floating diffusion region, and is converted to a voltage signal by output amplifier 3. It is this voltage signal produced by output amplifier 3 which is detected as an output signal. Output amplifier 3 is a charge sensing circuit including first drive transistor M1 of FIG. 1. The charge sensing circuit generally uses a source follower having a voltage gain close to unity. Reference numeral 4 denotes a precharge transistor.
FIG. 3 is a cross-sectional view taken along line III--III of FIG. 1. In FIG. 3, a P-type semiconductor layer 12 is formed over a N-type semiconductor substrate 11. A plurality of N-type regions 13 are formed in an array in the surface of semiconductor layer 12. An insulating layer 14, for example, a silicon oxide film, is deposited on the plurality of N-type region 13, and a plurality of transfer electrodes 15 are connected to form CCD transfer section 1 of FIG. 2.
Clock pulse signals .phi.1 and .phi.2 of alternating phases are provided as a driving pulse signal to selected N-type regions 13. Transfer electrodes 15, output gate electrode 17, and N.sup.+ type floating diffusion region 18 are formed in one end of CCD transfer section 1. Floating diffusion region 18 is connected to a gate electrode 19 of first drive MOS transistor M1 which constitutes a portion output amplifier 3.
In addition, a precharge drain region 23 is formed in the surface of semiconductor layer 12, such that a channel region 24 is apparent between floating diffusion region 18 and precharge drain region 23. Insulating layer 14 is deposited on the upper portion of a channel region 24 so as to form a precharge gate electrode 25. Thus, a precharge transistor having floating diffusion region 18 as a source region is formed.
The transfer and detection of electrical charge, as an output signal, will be described with reference to FIGS. 1 and 2. Initially, clock pulses .phi.1 and .phi.2 are applied to respective transfer electrodes 15 as shown in FIG. 3. In response to clock pulses .phi.1 and .phi.2, electrical charge is sequentially transferred from N-type regions 13 via a transfer channel formed in the surface of semiconductor substrate 11. Output gate 17 further transfers the electrical charge to floating diffusion region 18.
Floating diffusion region 18 is connected to output amplifier 3 which acts as a charge sensing or detecting circuit. Output amplifier 3 includes first drive MOS transistor M1, having gate electrode 19 connected to floating diffusion region 18 in order to sense the voltage level (i.e., electrical charge) of floating diffusion region 18. In addition to accumulating transferred charge, floating diffusion region 18 acts a source region for precharge transistor 4. Finally, drain region 23 of the precharge transistor is fixed by a predetermined voltage potential V.sub.PD.
A series of reset voltage pulses V.sub.PG are applied to precharge gate electrode 25 from an external reset pulse generator, and a precharge transistor is periodically turned ON so as to reset floating diffusion region 18 to voltage potential V.sub.PD supplied by precharge drain electrode 23. Accordingly, the electrical potential of floating diffusion region 18 is always "set" to V.sub.PD, as defined in precharge region 23, whenever precharge transistor 4 is turned ON. However, when precharge transistor 4 remains OFF electrical isolation between drain region 23 and floating diffusion region 18 is maintained until electrical signal charge is again accumulated in floating diffusion region 18.
As mentioned above, output amplifier 3 connected to floating diffusion region 18 detects a voltage change within this region, wherein the detected voltage is directly proportional to the amount of electrical charge accumulated in floating diffusion region 18, and is inversely proportional to the capacitance of the floating diffusion region 18. Any detected change in voltage is convened to a coherent image information signal by subsequent, well-known signal process circuitry.
A voltage change .DELTA. V.sub.OUT in output amplifier 3 can be expressed as follows. ##EQU1## where Q.sub.SIG is an amount of charge transferred to floating diffusion region 18, and C.sub.FD is the sum of capacitances associated with floating diffusion region 18, including parasitic capacitances.
Referring to FIG. 2 and the above equation, C.sub.FD =C.sub.B +C.sub.P +C.sub.O +C.sub.I +C.sub.IN, where C.sub.B is equal to the sum of the capacitance between floating diffusion region 18 and P-type semiconductor well 12, and the capacitance between floating diffusion region 18 and channel stopper region 22, C.sub.P is equal to the sum of capacitance C1 between floating diffusion region 18 and precharge gate electrode 25 and capacitance C2 between the precharge gate electrode 25 and the gate electrode 19 of first drive MOS transistor M1, C.sub.O is equal to the capacitance between floating diffusion region 18 and output gate 17, C.sub.I is equal to the capacitance between the adjacent wires in output amplifier 3, and C.sub.IN is equal to the input capacitance of output amplifier 3. Output voltage detection sensitivity for output amplifier 3 is determined by capacitance C.sub.FD and by the voltage gain A.sub.V of output amplifier 3. That is, detection sensitivity is the ratio of A.sub.V to C.sub.FD, and is expressed in terms of coulomb per volts.
Typical image sensors having the foregoing structure and operation have become increasingly integrated in recent years. While increased integration has several benefits including reduced size and power consumption, increased integration also proportionally reduces the light incident, pixel area of the image sensor. Accordingly, an amount of electrical charge Q.sub.SIG transferred to the floating diffusion region is decreased since the overall photoelectric conversion region is reduced by increased integration.
In order to effectively detect voltage variations associated with the accumulation of reduced electrical charge in contemporary image sensors, an voltage detection sensitivity must be improved. In order to dramatically improve detection sensitivity, the capacitance associated with floating diffusion region 18 must be significantly reduced. Specifically, input capacitance C.sub.IN, which accounts for a considerable portion of capacitance C.sub.FD, must be significantly reduced.
FIG. 4 is another cross-sectional view of FIG. 1 taken along line IV--IV, which illustrates a charge sensing circuit, i.e., first drive MOS transistor M1 of output amplifier 3 within the CCD image sensor having a conventional FDA. As shown in FIG. 4, gate electrode 19 partially overlaps each one of opposing gate source region 20 and drain region 21. This structure results in first drive MOS transistor M1 having a parasitic capacitance C.sub.m between overlapping gate electrode 19 and source region 20, and another parasitic capacitance C.sub.d between overlapping gate electrode 19 and drain region 21. C.sub.m and C.sub.d significantly increase input capacitance C.sub.IN of output amplifier 3. Parasitic capacitance C.sub.m can be compensated by the Miller effect according to the driving operation of first drive MOS transistor M1. This is not the case for parasitic capacitance C.sub.d. Thus, C.sub.in of output amplifier 3 is increased by C.sub.d, and a detection sensitivity of a signal detecting section incorporating output amplifier 3 is proportionally degraded.